1. Field of Invention
This invention relates to analog-to-digital converters. Specifically, the present invention relates to high-performance delta sigma analog-to-digital converters.
2. Description of the Related Art
Analog-to-digital converters (ADC""s) are employed in a variety of demanding applications including computer modems, wireless telephones, and satellite receiver systems. Such applications demand cost-effective ADC""s that can efficiently convert an analog input signal to digital output signal over a wide range of frequencies and signal magnitudes with minimal noise and distortion.
An ADC typically converts an analog signal to a digital signal by sampling the analog signal at predetermined sampling intervals and generating a sequence of binary numbers via a quantizer in response thereto. The sequence of binary numbers is a digital signal representation of the sampled analog signal.
The length of a binary number assigned to a given sampled value of the analog signal corresponds to the number of quantizer bits and is limited. Consequently, a digital sample will not always precisely represent the corresponding analog sample. The difference between a digital sample and the corresponding analog sample represents quantization error.
The sampling frequency of the ADC is the inverse of the sampling interval. The resolution of the ADC is directly related to the number of binary bits assigned to each sampled value and inversely related to quantization error. The minimum difference between successive values that may be represented by the quantizer is the quantization step size. Quantization error results in quantization noise in the output digital signal, which is also called granular noise.
When an analog sample is too large to be accurately digitally represented by to the quantizer (given the fixed number of quantizer bits), clipping occurs, resulting in distortion called overload noise. To reduce overload noise, the dynamic range of an ADC is often increased. The dynamic range of an ADC is the range of values of an analog input signal over which the ADC can accurately represent the analog signal. For a conventional Nyquist ADC, the dynamic range is difference between maximum and minimum values represented by the quantizer. High-quality ADC""s often have high signal-to-noise ratios (SNR""s) and high dynamic ranges.
The sampling frequency of an ADC is usually chosen to be greater than twice the maximum frequency of the analog input signal, which is known as the Nyquist rate. In a typical Nyquist ADC, the input analog signal is sampled at approximately the Nyquist rate. To achieve effective SNR""S, the resolution of the ADC is increased.
Unfortunately, adding additional resolution required to obtain sufficient SNR""s is often costly.
Alternatively, oversampling ADC""s are employed. An oversampling ADC samples an analog signal at sufficiently high rates to reduce quantizer resolution requirements. By oversampling, differences between signal values of successive samples are reduced, which reduces resolution requirements. Unfortunately, typical oversampling ADC""s are still particularly susceptible to overload distortion and granular noise.
A delta sigma (xcex94xcexa3) modulator ADC (xcex94xcexa3 ADC) sufficiently oversamples a given analog input signal so that only one quantizer bit is required. Some xcex94xcexa3 ADC""s however, employ multi-bit quantizers to fuirther reduce quantization noise. A continuous time xcex94xcexa3 ADC (also known as a sigma-delta modulator ADC) typically includes a continuous time loop filter having integrators and transconductance amplifiers, which implements a bandpass loop filter and/or resonator, to reduce granular noise and overload distortion. The xcex94xcexa3 ADC includes one or more feedback loops, which include multi-bit feedback DAC""s, to avoid the accumulation of quantization errors and to stabilize the xcex94xcexa3 ADC.
Unfortunately, conventional xcex94xcexa3 ADC""s are often difficult to implement and are susceptible to noise resulting from delays in the quantizer feedback path. The delays include signal dependent jitter delay, latch delay, and DAC cell switching delays. To compensate for the excess latch delay, a plurality of additional multi-bit return-to-zero (RZ) digital-to-analog converters (DAC""s) are selectively placed in the quantizer feedback path. (The RZ DAC""s are DAC""s whose outputs periodically reset to zero.) However, the additional RZ DAC""s are often expensive and difficult to implement accurately. At the high sampling rates required for xcex94xcexa3 ADC""s, the RZ DAC""s in the quantizer feedback path may have insufficient time to settle to zero, resulting in poor ADC performance. For performance reasons, more cost-effective non-return-to-zero (NRZ) DAC""s are typically not substituted in place of the RZ DAC""s in conventional xcex94xcexa3 ADC designs.
In an alternative approach, some feedback delays are compensated via a combination of non-delayed and half-delayed appropriately tuned feedback DAC""s. However, this approach still fails to effectively compensate for signal dependent jitter and other delays.
Finite DAC cell switching delays in the multi-bit feedback DAC""s are also problematic. As is known in the art, multi-bit DAC""s have hardware limitations that result in glitches in signal output by circuits employing these devices. Glitches result when less than all of the bits in a DAC change simultaneously. Hence, the output waveform exhibits temporary false values as the bits change to their appropriate values. The glitches cause spurious frequency tones, i.e., glitch noise, to appear at the DAC output very close to the desired output frequency. The spurious tones can degrade the performance of the accompanying xcex94xcexa3 ADC. Unmatched DAC cell switching delays reduce the dynamic range of the accompanying xcex94xcexa3 ADC and adversely affect circuit stability, especially in fourth order or higher order xcex94xcexa3 ADC""s. The order of a given xcex94xcexa3 ADC is related to the number of resonating frequencies in the loop filter of the xcex94xcexa3 ADC.
The output of a feedback DAC also includes quantization noise that is directly related to the DAC""s amplitude resolution. The number of bits used in the DAC computations determines amplitude resolution. DAC""s with excellent amplitude resolution and frequency response tend to consume excess power and are expensive. In addition, spurious tones become more problematic as the frequency of the periodic signal increases. This further limits the range of allowable output frequencies.
Some conventional xcex94xcexa3 ADC""s employ a high-speed flash quantizer, which includes multiple comparators for comparing sampled signal values to particular reference thresholds corresponding to quantization levels. A given sampled signal value is closer to the thresholds of some comparators than others. Consequently, the quantizer comparators switch and regenerate at different times, which results in undesirable signal dependent jitter delay.
Conventional xcex94xcexa3 ADC""s employing RZ DAC""s often fail to address signal dependent jitter. Signal dependent jitter is an additional source of loop delay in the quantizer feedback path. The additional loop delay reduces the dynamic performance of the ADC and may reduce feedback loop stability. An ADC with good dynamic performance accurately represents a given analog signal over a wide range of values and frequencies.
Hence, a need exists in the art for a cost-effective high-performance xcex94xcexa3 ADC that effectively compensates for quantizer feedback loop delays, including signal dependent jitter, latch delay, and finite DAC cell switching delay.
The need in the art is addressed by the high-performance analog-to-digital converter of the present invention. In the illustrative embodiment, the inventive analog-to-digital converter is a delta sigma modulator analog-to-digital converter and includes a first mechanism for converting an input analog signal to a digital output signal. The first mechanism is characterized by a noise transfer function that is altered relative to an ideal noise transfer function. A second mechanism compensates for the alteration in the transfer function via a single additional digital-to-analog converter.
In a specific embodiment, the alteration includes an additional pole and an additional zero included in the transfer function relative to the ideal noise transfer function. The alteration is induced by feedback delays in the first mechanism. The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism includes an additional latch for compensating for the signal dependent jitter delay.
The first mechanism includes a resonator and a quantizer. The second mechanism includes a quantizer-DAC feedback path from an output of the quantizer to the resonator. The feedback path includes a first latch positioned between an output of the quantizer and the additional digital-to-analog converter. The feedback path further includes an additional latch positioned at an output of the first latch. The additional latch eliminates signal dependent jitter delay in the analog-to-digital converter. The digital-to-analog converter is a non-return-to-zero digital-to-analog converter. An output of the digital-to-analog converter is connected to the resonator.
The novel design of the present invention is facilitated by the second mechanism, which includes an additional feedback digital-to-analog converter and an additional latch for compensating for signal dependent jitter delay and digital-to-analog converter cell switching delay. By compensating for the various feedback delays, the delta sigma modulator digital-to-analog converter of the present invention affords improved stability and dynamic range performance.